What is I/O APIC?

What is I/O APIC?

IOAPIC The Intel I/O Advanced Programmable Interrupt Controller is used to distribute external interrupts in a more advanced manner than that of the standard 8259 PIC. With the I/O APIC, interrupts can be distributed to physical or logical (clusters of) processors and can be prioritized. Each I/O APIC typically handles 24 external interrupts.

How many I/O APICs can I have?

Parsing will tell how many (if any) I/O APICs exist, what are their APIC ID, base MMIO address and first IRQ (or GSI – Global System Interrupt). For more information on parsing the MP tables, see the External MP Tables Links section below. So you can have, say, 2 I/O APICs, the first handling IRQs 0 – 23 and the second 24 – 47.

How to identify I/O APICs with an entry 0x02?

In the MP tables, configuration tables with the entry identification of 0x02 are for I/O APICs. Parsing will tell how many (if any) I/O APICs exist, what are their APIC ID, base MMIO address and first IRQ (or GSI – Global System Interrupt).

How many pins are there in an ioapic?

A typical IOAPIC has 24 pins, pin 0-15 are* used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and* some BIOSes may use MP Interrupt Source records to override IRQ numbers for* PIRQs instead of reprogramming the interrupt routing logic.