What is an AXI Stream?

The AXI4-Stream protocol is used as a standard interface to connect components that wish to exchange data. The interface can be used to connect a single master, that generates data, to a single slave, that receives data. The protocol can also be used when connecting larger numbers of master and slave components.

What is AXI in Xilinx?

AXI, which means Advanced eXtensible Interface, is an interface protocol defined by ARM as par of the AMBA (Advanced Microcontroller Bus Architecture) standard. The AXI3/AXI4 specification are freely-available on the ARM website (link) so I encourage anybody who is interested to download it.

What is Tlast AXI Stream?

(1) TLAST is used by most of the Xilinx blocks to indicate the end of a stream. In the DMA, it’s the end of a transfer. In the VDMA, it’s the end of a line.

What is an AXI interconnect?

The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from ARM®, including the AXI4-Lite control register interface subset.

What is the use of AXI?

The AXI is a point to point interconnect that designed for high performance, high speed microcontroller systems. The AXI protocol is based on a point to point interconnect to avoid bus sharing and therefore allow higher bandwidth and lower latency. AXI is arguably the most popular of all AMBA interface interconnect.

What does AXI stand for?

The Advanced eXtensible Interface (AXI), is an on-chip communication bus protocol developed by ARM. It is part of the Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications.

What is AXI Lite?

AXI4-Lite is a subset of the AXI4 protocol, providing a register-like structure with reduced features and complexity. Notable differences are: all bursts are composed by 1 beat only. all data accesses use the full data bus width, which can be either 32 or 64 bits.

How many slaves can be connected to AXI?

16 Slave Interfaces
“Up to 16 Slave Interfaces (to accept transactions from up to 16 connected Master Devices) and one Master Interface (to issue transactions to one connected Slave Device).” Therefore, the CORE Generator version of the AXI Interconnect can support 16 Master Devices and 1 Slave Device.

What is AXI full form?

The Advanced eXtensible Interface (AXI), is an on-chip communication bus protocol developed by ARM.